NXP Semiconductors MPC5606S - Setting of the PRESCALE Register

Stepper Stall Detect (SSD)
MPC5606S Microcontroller Reference Manual, Rev. 7
1180 Freescale Semiconductor
Figure 36-15. Current flow for Integration (STEP = 2, ITGDCL = 1)
Figure 36-16 below shows that the sine coil is driven for STEP = 3 in reverse direction with respect to
STEP = 1 (M  P direction). Again the other coil (cosine) is isolated from the analog supply voltages
because it is the integration phase of the current BIS.
Figure 36-16. Current flow for Integration (STEP = 3, ITGDCL = 1)
36.6.2 Setting of the PRESCALE Register
36.6.2.1 Timing Resolution Considerations
Set the ACDIV bits to the lowest division factor possible, resulting in the highest possible clock frequency
for the integration accumulator. This will give the most precise result.
VDDM
COSP COSM
T1
T2
T3
T4
VSSM
VDDM
SINP SINM
T5
T6
T7
T8
VSSM
VDDM
COSP COSM
T1
T2
T3
T4
VSSM
VDDM
SINP SINM
T5
T6
T7
T8
VSSM