NXP Semiconductors MPC5606S - THRESHOLD_INP_BUF_1 Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 389
12.3.4.30 THRESHOLD_INP_BUF_1 Register
Figure 12-39 shows the threshold register for input buffer.
Figure 12-39. Threshold input buffer 1 Register (THRESHOLD_INP_BUF_1)
12.3.4.31 THRESHOLD_INP_BUF_2 Register
Figure 12-40 represents the threshold register for input buffer for plane 3 and plane 4.
30
M_L1_parr_err
M_L1_parr_err interrupt mask
0 Do not mask the interrupt
1 Mask the interrupt
31
M_L0_parr_err
M_L0_parr_err interrupt mask
0 Do not mask the interrupt
1 Mask the interrupt
Offset: 0x234 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
INP_BUF_p2_hi INP_BUF_p2_lo
W
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INP_BUF_p1_hi INP_BUF_p1_lo
W
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Table 12-34. THRESHOLD_INP_BUF_1 field descriptions
Field Description
0–7
INP_BUF_p2_hi
High Threshold for input buffer for blend stage 2.
8–15
INP_BUF_p2_lo
Low Threshold for input buffer for blend stage 2.
16–23
INP_BUF_p1_hi
High Threshold for input buffer for blend stage 1 (background).
24–31
INP_BUF_p1_lo
Low Threshold for input buffer for blend stage 1 (background plane).
Table 12-33. Mask parameter error status register field descriptions (continued)
Field Description