Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 529
16.4.2.6.1 XBAR_lite force_round_robin bit (MUDCR[31])
When the XBAR_lite is included on the platform, this bit is used to drive the force_round_robin bit of the
XBAR_lite. This will force the slaves into round robin mode of arbitration rather than fixed mode.
However, the situation is different if a master is using priority elevation, which forces the design back into
fixed mode regardless of this bit. By defining the define ENABLE_ROUND_ROBIN_RESET, this bit will
reset to 1.
16.4.2.7 ECC registers
For designs including error-correcting code (ECC) implementations to improve the quality and reliability
of memories, there are a number of program-visible registers for the sole purpose of reporting and logging
memory failures. These optional registers include:
• ECC Configuration Register (ECR)
• ECC Status Register (ESR)
• ECC Error Generation Register (EEGR)
• Flash ECC Address Register (FEAR)
• Flash ECC Master Number Register (FEMR)
• Flash ECC Attributes Register (FEAT)
• Flash ECC Data Register (FEDR)
• RAM ECC Address Register (REAR)
• RAM ECC Syndrome Register (RESR)
• RAM ECC Master Number Register (REMR)
• RAM ECC Attributes Register (REAT)
• RAM ECC Data Register (REDR)
The details on the ECC registers are provided in the subsequent sections. If the design does not include
ECC on the memories, these addresses are reserved locations within the ECSM programming model.
16.4.2.8 ECC Configuration Register (ECR)
The ECC Configuration Register is an 8-bit control register for specifying which types of memory errors
are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access
to be terminated with an error condition. In many cases, this error termination is reported directly by the
initiating bus master.
However, there are certain situations where the occurrence of this type of non-correctable error is not
reported by the master. Examples include speculative instruction fetches which are discarded due to a
change-of-flow operation, and buffered operand writes. The ECC reporting logic in the ECSM provides
an optional error interrupt mechanism to signal all non-correctable memory errors. In addition to the
interrupt generation, the ECSM captures specific information (memory address, attributes and data, bus
master number, etc.) which may be useful for subsequent failure analysis.
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