LIN Controller (LINFlex)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 835
Figure 23-5. LINFlex in Self-test mode
23.7 Memory map and registers description
23.7.1 Memory map
The base addresses for the LINFlex modules are as follows:
• 0xFFE4_0000 (LINFlex_0)
• 0xFFE4_4000 (LINFlex_1)
Table 23-2 shows the LINFlex memory map.
Table 23-2. LINFlex memory map
Offset from
LINFLEX_BASE
Register
Access
Reset value Location
0x0000 LIN control register 1 (LINCR1) R/W See note
1
on page 837
0x0004 LIN interrupt enable register (LINIER) R/W 0x0000_0000 on page 840
0x0008 LIN status register (LINSR) R/W 0x0000_0080 on page 842
0x000C LIN error status register (LINESR) R/W 0x0000_0000 on page 845
0x0010 UART mode control register (UARTCR) R/W 0x0000_0000 on page 846
0x0014 UART mode status register (UARTSR) R/W 0x0000_0000 on page 848
0x0018 LIN timeout control status register (LINTCSR) R/W 0x0000_0040 on page 850
0x001C LIN output compare register (LINOCR) R/W 0x0000_FFFF on page 851
0x0020 LIN timeout control register (LINTOCR) R/W See note
2
on page 851
0x0024 LIN fractional baud rate register (LINFBRR) R/W 0x0000_0000 on page 852
0x0028 LIN integer baud rate register (LINIBRR) R/W 0x0000_0000 on page 853
0x002C LIN checksum field register (LINCFR) R/W 0x0000_0000 on page 854
0x0030 LIN control register 2 (LINCR2) R/W See note
3
on page 854
0x0034 Buffer identifier register (BIDR) R/W 0x0000_0000 on page 856
0x0038 Buffer data register LSB (BDRL)
4
R/W 0x0000_0000 on page 857
LINFlex
LINTX LINRX
Tx Rx
=1
To Next Page
Loading...
