NXP Semiconductors MPC5606S - LUMA Component Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
390 Freescale Semiconductor
Figure 12-40. THRESHOLD_INP_BUF_2 Register
12.3.4.32 LUMA Component Register
Figure 12-41 represents the LUMA component register.
Figure 12-41. LUMA Component Register
Offset: 0x238 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
INP_BUF_p4_hi INP_BUF_p4_lo
W
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INP_BUF_p3_hi INP_BUF_p3_lo
W
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Table 12-35. THRESHOLD_INP_BUF_2 field descriptions
Field Description
0–7
INP_BUF_p4_hi
High Threshold for input buffer for blend stage 4.
8–15
INP_BUF_p4_lo
Low Threshold for input buffer for blend stage 4.
16–23
INP_BUF_p3_hi
High Threshold for input buffer for blend stage 3.
24–31
INP_BUF_p3_lo
Low Threshold for input buffer for blend stage 3.
Offset: 0x23C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Y_RED
0
Y_GREEN[0:4]
W
Reset 1 0 0 1 0 1 0 1 0 0 0 1 0 0 1 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Y_GREEN[5:9]
0
Y_BLUE
W
Reset 1 0 1 0 0 0 1 0 0 1 0 1 0 1 0 0