Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 649
The PFLASH2P_LCA generates three sets of interface signals for the flash banks, including read and write
enables, the flash array address, write size, and write data as inputs to each flash bank. The
PFLASH2P_LCA captures read data from the flash banks and drives it onto the AHB. Each flash bank
includes data storage for fetched pages on a per AHB port basis, either in the form of 4-entry page buffers
(banks 0 and 2) or a 1-entry temporary holding register (bank 1). Pages may be prefetched in advance of
being requested by the AHB interface, allowing single-cycle (zero AHB wait-states) read data responses
on buffer hits.
Multiple prefetch control algorithms are available for controlling page read buffer fills. Prefetch triggering
may be restricted to instruction accesses only, data accesses only, or may be unrestricted. Prefetch
triggering may also be controlled on a per-master basis.
Buffers may also be selectively enabled or disabled for allocation by instruction and data prefetch.
Access protections may be applied on a per-master basis for both reads and writes to support security and
privilege mechanisms.
Recall the logic of the PFLASH2P_LCA is structured to support simultaneous AHB accesses from the two
ports fully in parallel when the references are targeted to different memory banks. If simultaneous AHB
accesses reference the same bank, then arbitration logic within the PFLASH2P_LCA determines the order
the references are granted access to the bank. For more information, see Section 17.4.4.10, Input port
arbitration.
17.4.4.1 Access protections
The PFLASH2P_LCA provides programmable configurable access protections for both read and write
cycles from masters via the PFLASH Access Protection Register (PFAPR). It allows restriction of read and
write requests on a per-master basis. This functionality is described in Section 17.4.3.2.3, Platform Flash
Access Protection Register (PFAPR). Detection of a protection violation results in an error response from
the PFLASH2P_LCA on the AHB transfer.
17.4.4.2 Read cycles—buffer miss
Read cycles from the flash array are initiated by driving a valid access address on bkn_fl_addr[23:0] and
asserting bkn_fl_rd_en for the required setup (and hold) time before (and after) the rising edge of hclk. The
PFLASH2P_LCA then waits for the programmed number of read wait states before sampling the read data
on bkn_fl_rdata[127:0]. This data is normally stored in the least-recently updated page read buffer for
banks 0 and 2 in parallel with the requested data being forwarded to the AHB. For bank1, the data is
captured in the page-wide temporary holding register as the requested data is forwarded to the AHB bus.
Timing diagrams of basic read accesses from the flash array are shown in Figure 17-47 through
Figure 17-50.
If the flash access was the direct result of an AHB transaction, the page buffer is marked as
most-recently-used as it is being loaded. If the flash access was the result of a speculative prefetch to the
next sequential line, it is first loaded into the least-recently-used buffer. The status of this buffer is not
changed to most-recently-used until a subsequent buffer hit occurs.
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