Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 731
20.4 Memory map and register description
20.4.1 Overview
This section provides a detailed description of all memory-mapped registers in the I
2
C module.
20.4.2 Module memory map
The memory map for the I
2
C module is given below in Table 20-1. The total address for each register is
the sum of the base address for the I
2
C module and the address offset for each register.
All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned
to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, the IBDF
register for the frequency divider is accessible by a 16-bit READ/WRITE to address Base + 0x000, but
performing a 16-bit access to Base + 0x001 is illegal.
20.4.3 Register description
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
Table 20-1. Module memory map
Address Register
Size
(bits)
Access Mode
1
1
U = User mode, S = Supervisor mode, A = All (No restrictions)
Location
Base + 0x00 I
2
C Bus Address Register (IBAD) 8 R/W A on page 732
Base + 0x01 I
2
C Bus Frequency Divider Register (IBFD) 8 R/W A on page 732
Base + 0x02 I
2
C Bus Control Register (IBCR) 8 R/W A on page 738
Base + 0x03 I
2
C Bus Status Register (IBSR) 8 R/W A on page 739
Base + 0x04 I
2
C Bus Data I/O Register (IBDR) 8 R/W A on page 740
Base + 0x05 I
2
C Bus Interrupt Configuration Register
(IBIC)
8 R/W A on page 741
Base + 0x06 Unused 8 R A —
Base + 0x07 Unused 8 R A —
Base + 0x08 –
Base + 0x3FFF
Reserved See Note
2
2
If enabled at the SoC level, reads or writes to these registers will cause bus aborts. Refer to the System Services
Module documentation for more details.
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