Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
546 Freescale Semiconductor
The module is a non-volatile solid-state silicon memory device consisting of blocks (called also sectors)
of single transistor storage elements, an electrical means for selectively adding (programming) and
removing (erasing) charge from these elements, and a means of selectively sensing (reading) the charge
stored in these elements.
The flash module is arranged as two functional units: the flash core and the memory interface.
The flash core is composed of arrayed non-volatile storage elements, sense amplifiers, row decoders,
column decoders, and charge pumps. The arrayed storage elements in the Flash Core are subdivided into
physically separate units referred to as blocks (or sectors).
The memory interface contains the registers and logic which control the operation of the flash core. The
memory interface is also the interface between the flash module and a Bus Interface Unit (BIU) and
contains the ECC logic and redundancy logic.
A BIU connects the flash module to a system bus, and contains all system-level customization required for
the SoC application.
17.2.2 Main features
• High read parallelism (128 bits)
• Error Correction Code (SEC-DED) to enhance data retention
• Double-word program (64 bits)
• Sector Erase
• Double bank (code flash 0 and code flash 1): allows one bank to be read while the other bank is
being modified
• Erase suspend available (program suspend not available)
• Software programmable program/erase protection to avoid unwanted writes
• Censored mode against piracy
• Usable as main code memory of the SoC
• Shadow block available
• One-time programmable (OTP) area in Test flash block
17.2.3 Block diagram
Each bank contains one flash macrocell comprising one matrix module, normally used for code storage.
No Read-While-Modify operations are possible within the same bank.
The modify operations are managed by an embedded Flash Program/Erase Controller (FPEC). Commands
to the FPEC are given through a User Registers Interface.
The read data bus is 128 bits wide, while the flash memory registers are on a separate 32-bit bus addressed
in the user memory map.
The high voltages needed for program/erase operations are internally generated.
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