Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
600 Freescale Semiconductor
When exiting from Low-Power mode the flash memory module returns to its previous state in all cases
unless it was in the process of executing an erase high voltage operation at the time of entering Low-Power
mode.
If the flash memory module enters Low-Power mode during an erase operation, the MCR[ESUS] bit is set.
The user may resume the erase operation when the module exits Low-Power mode by clearing the
MCR[ESUS] bit. The MCR[EHV] bit must be high to resume the erase operation.
If the flash memory module is configured to enter Low-Power mode during a program operation, the
operation will be completed and the Low-Power mode will be entered only after the programming ends.
It is forbidden to enter Power-Down mode when the Low-Power mode is active.
17.3.6 Register description
The flash memory user registers mapping is shown in the following table.
In the following some non-volatile registers are described. Please notice that such entities are not
Flip-Flops, but locations of Test flash sector with a special meaning.
During the flash memory initialization phase, the FPEC reads these non-volatile registers and update their
related Volatile Registers. When the FPEC detects ECC double errors in these special locations, it behaves
in the following way:
Table 17-40. Flash 528 KB single bank registers
Register name Address Offset Location
Module Configuration Register (MCR) 0x00 on page 601
Low/mid Address Space Block Locking Register (LML) 0x04 on page 605
High Address Space Block Locking Register (HBL) 0x08 on page 608
Secondary Low/Mid Address Space Block Lock Register (SLL) 0x0C on page 609
Low/mid Address Space Block Select Register (LMS) 0x10 on page 612
High Address Space Block Select Register (HBS) 0x14 on page 613
Address Register (ADR) 0x18 on page 614
Reserved 0x1C–0x3B —
User Test Register 0 (UT0) 0x3C on page 616
User Test Register 1 (UT1) 0x40 on page 618
User Test Register 2 (UT2) 0x44 on page 618
User Multiple Input Signature Register 0 (UMISR0) 0x48 on page 619
User Multiple Input Signature Register 1 (UMISR1) 0x4C on page 620
User Multiple Input Signature Register 2 (UMISR2) 0x50 on page 620
User Multiple Input Signature Register 3 (UMISR3) 0x54 on page 621
User Multiple Input Signature Register 4 (UMISR4) 0x58 on page 622
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