Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 729
Chapter 20
Inter-Integrated Circuit Bus Controller Module (I
2
C)
20.1 Introduction
20.1.1 Overview
The Inter-Integrated Circuit (I
2
C™ or IIC) bus is a two wire bidirectional serial bus that provides a simple
and efficient method of data exchange between devices. It minimizes the number of external connections
to devices and does not require an external address decoder.
This bus is suitable for applications requiring occasional communications over a short distance between a
number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for
further expansion and system development.
The interface is designed to operate up to 100 kbit/s with maximum bus loading and timing. The device is
capable of operating at higher baud rates, up to a maximum of module clock/20, with reduced bus loading.
The maximum communication length and the number of devices that can be connected are limited by a
maximum bus capacitance of 400 pF.
20.1.2 Features
The I
2
C module has the following key features:
• Compatible with I
2
C Bus standard
• Multi-master operation
• Software programmable for one of 256 different serial clock frequencies
• Software selectable acknowledge bit
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated start signal generation
• Acknowledge bit generation/detection
• Bus busy detection
Features currently not supported:
• No support for general call address
• Not compliant to ten-bit addressing
20.1.3 Block diagram
The block diagram of the I
2
C module is shown in Figure 20-1.
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