Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
542 Freescale Semiconductor
16.4.3 High-priority enables
e200 processors can be configured to support critical and/or external interrupts. Furthermore, each
processor can be configured to employ priority elevation on critical and/or external interrupt events.
Critical interrupts come from outside the platform, and are routed directly to the processor’s critical
interrupt input. External interrupts are routed through the interrupt controller. In addition to the interrupt
notification signals, various processor-specific configuration flags from the processor’s Machine Check
Register (MCR[ee,ce]) and the Hardware Implementation Register (HID1) are sent to the ECSM to
determine when interrupt servicing is enabled and when high-priority elevation should be enabled. If the
corresponding processor is configured to allow high-priority elevation on critical interrupt events, the
ECSM generates the high-priority signal upon critical interrupt detection and holds it active throughout
the duration of interrupt servicing. If the corresponding processor is configured to allow high-priority
elevation on external interrupt events, the ECSM generates the high-priority signal upon external interrupt
detection and holds it active throughout the duration of interrupt servicing. During interrupt servicing the
processor status output, p_stat, is monitored for indication of a return from interrupt (rfi).
Great care needs to be taken when using the priority elevation as it can enable a master to starve the rest
of the masters in the system. Please see Chapter 10, Crossbar Switch (XBAR), for information on priority
elevation.
16.4.4 Spp_ips_reg_protection
The spp_ips_reg_protection logic provides hardware enforcement of supervisor mode access protection
for five on-platform IPS modules: INTC, ECSM, MPU, STM, and SWT. This logic resides between the
on-platform bus sourced by the PBRIDGE bus controller and the individual slave modules. It monitors the
bus access type (supervisor or user) and if a user access is attempted, the transfer is terminated with an
error and inhibited from reaching the slave module. Identical logic is replicated for each of the five targeted
slave modules. A block diagram of the spp_ips_reg_protection module is shown in Figure 16-19.
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