Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 657
Note that the wait-state specification consists of two components: haddr[28:26] and haddr[25:24] and
effectively extends the flash read by (8 * haddr[25:24] + haddr[28:26]) cycles.
Table 17-69 shows the relationship of haddr[25:24] to the number of additional wait-states. These are
applied in addition to those specified by haddr[28:26] and thus extend the total wait-state specification
capability.
17.4.4.13 Timing diagrams
Since PFLASH2P_LCA controller is typically used in platform configurations with a cacheless core, the
operation of the processor accesses to the platform memories, e.g., flash and SRAM, plays a major role in
the overall system performance. Given the core/platform pipeline structure, the platform’s memory
controllers (PFLASH, PRAM) are designed to provide a zero wait-state data phase response to maximize
processor performance. The following diagrams illustrate operation of various cycle types and responses
referenced earlier in this chapter including stall-while-read (Figure 17-51) and abort-while-read
(Figure 17-52) diagrams.
Table 17-68. Additional Wait-State encoding
Memory Address
haddr[28:26]
Additional wait-states
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
Table 17-69. Extended additional Wait-State encoding
Memory address
haddr[25:24]
Additional Wait-states
(added to those specified by haddr[28:26])
00 0
01 8
10 16
11 24
To Next Page
Loading...
