NXP Semiconductors MPC5606S - Modes of Operation

Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
308 Freescale Semiconductor
shift register of the slave, and vice versa. At the end of a transfer, the TCF bit in the DSPIx_SR is set to
indicate a completed transfer. Figure 11-11 illustrates how master and slave data are exchanged.
Figure 11-11. SPI serial protocol overview
The DSPI has three peripheral chip select (CSx) signals that select the slaves with which to communicate.
Transfer protocols and timing properties are shared by the three DSPI configurations; these properties are
described independently of the configuration in Section 11.8.5, Transfer formats. The transfer rate and
delay settings are described in section Section 11.8.4, DSPI baud rate and clock delay generation.
Refer to Section 11.8.8, Power-saving features, for information on the power-saving features of the DSPI.
11.8.1 Modes of operation
The DSPI modules have five available distinct modes:
• Master mode
• Slave mode
• Module Disable mode
• External stop mode
• Debug mode
Master, Slave, and Module Disable modes are module-specific modes. The external stop and debug modes
are device-specific modes.
The module-specific modes are determined by bits in the DSPIx_MCR. The device-specific modes are
modes that the entire device can enter in parallel with the DSPI being configured in one of its
module-specific modes.
11.8.1.1 Master mode
In Master mode, the DSPI can initiate communications with peripheral devices. The DSPI operates as bus
master when the MSTR bit in the DSPIx_MCR is set. The serial communications clock (SCK) is
controlled by the master DSPI. All three DSPI configurations are valid in Master mode.
In SPI configuration, Master mode transfer attributes are controlled by the SPI command in the current TX
FIFO entry. The CTAS field in the SPI command selects which of the eight DSPIx_CTARs are used to set
the transfer attributes. Transfer attribute control is on a frame-by-frame basis.
Refer to Section 11.8.3, Serial Peripheral Interface (SPI) configuration, for more details.
DSPI Master
Shift register
Baud rate generator
DSPI Slave
Shift register
SOUT_x
SIN_x
SOUT_x SIN_x
SCK_x SCK_x
CS_x CS0_x