Safety
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 119
In the example in Figure 4-10, addresses 0x0C and 0x0D are unprotected. Therefore their corresponding
lock bits SLBR3.SLB[1:0] are always 0b0 (shown in bold). When doing a 32-bit write access to address
0x200C, only lock bits SLBR3.SLB[3:2] are set while bits SLBR3.SLB[1:0] stay 0b0.
NOTE
Lock bits can only be set via writes to the mirror module space. Reads from
the mirror module space will not change the lock bits.
4.1.4.2.3 Write protection for locking bits
Changing the locking bits through any of the procedures mentioned in Section 4.1.4.2.1, Change lock
settings directly via area #4, and Section 4.1.4.2.2, Enable locking via mirror module space (area #3), is
only possible as long as the bit GCR.HLB is cleared. Once this bit is set the locking bits can no longer be
modified until after a system reset.
4.1.4.3 Access errors
The protection module generates transfer errors under several circumstances. For the area definition refer
to Figure 4-2.
1. If accessing area #1 or area #3, the protection module will pass on any access error from the
underlying Module under Protection.
2. If user mode is not allowed, user writes to all areas will assert a transfer error and the writes will
be blocked.
3. If accessing the reserved area #2, a transfer error will be asserted.
4. If accessing unimplemented 32-bit registers in area #4 and area #5 a transfer error will be asserted.
5. If writing to a register in area #1 and area #3 with Soft Lock Bit set for any of the affected bytes, a
transfer error is asserted and the write will be blocked. Also the complete write operation to
non-protected bytes in this word is ignored.
6. If writing to a Soft Lock Register in area #4 with the Hard Lock Bit being set, a transfer error is
asserted.
7. Any write operation in any access mode to area #3 while Hard Lock Bit GCR.HLB is set.
4.1.5 Reset
The reset state of each individual bit is shown within the Register description section (See Section 4.1.3.2,
Register description). In summary, after reset, locking for all MRn registers is disabled. The registers can
be accessed in Supervisor mode only.
4.2 Software Watchdog Timer (SWT)
4.2.1 Overview
The Software Watchdog Timer (SWT) is a peripheral module that can prevent system lockup in situations
such as software getting trapped in a loop or if a bus transaction fails to terminate. When enabled, the SWT
To Next Page
Loading...
