NXP Semiconductors MPC5606S - Emios200 UC Counter Register (Emioscnt[N])

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
248 Freescale Semiconductor
9.4.2.7 eMIOS200 UC Counter Register (EMIOSCNT[n])
The EMIOSCNT[n] register contains the value of the internal counter. When GPIO mode is selected or the
channel is frozen, the EMIOSCNT[n] register is read/write. For all others modes, the EMIOSCNT[n] is a
read-only register. When entering some operation modes, this register is automatically cleared. See
Section 9.5.1.1, UC modes of operation, for details.
Depending on the channel configuration, it may or may not have the EMIOSCNT register. The
EMIOSCNT register is required for the following modes: OPWFMB and MCB.
It is possible that, for particular reasons, EMIOSCNT may be available on one device even if the respective
channel does not feature any mode that requires it. In this case, EMIOSCNT availability should be
explicitly described in the device SoC guide.
9.4.2.8 eMIOS200 UC Control Register (EMIOSC[n])
The Control register gathers bits reflecting the status of the UC input/output signals and the overflow
condition of the internal counter, as well as several read/write control bits.
Address: UC[n] base address + 0x08 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
1
1
In GPIO mode or freeze action, this register is writable.
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RC
W
1
Reset0000000000000000
Figure 9-14. eMIOS200 UC Counter Register (EMIOSCNT[n])