IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 727
19.9.3 e200z0 OnCE controller register description
Most e200z0 OnCE debug registers are fully documented in the e200z0 Reference Manual.
19.9.3.1 OnCE Command Register (OCMD)
The OnCE command register (OCMD) is a 10-bit shift register that receives its serial data from the TDI
pin and serves as the instruction register (IR). It holds the 10-bit commands to be used as input for the
e200z0 OnCE Decoder. The OCMD is shown in Table 19-5. The OCMD is updated when the TAP
controller enters the Update-IR state. It contains fields for controlling access to a resource, as well as
controlling single-step operation and exit from OnCE mode.
Although the OCMD is updated during the Update-IR TAP controller state, the corresponding resource is
accessed in the DR scan sequence of the TAP controller, and as such, the Update-DR state must be
transitioned through in order for an access to occur. In addition, the Update-DR state must also be
transitioned through in order for the single-step and/or exit functionality to be performed, even though the
command appears to have no data resource requirement associated with it.
0 1 2 3 4 5 6 7 8 9
R
R/W GO EX RS[0:6]
W
Reset: 0 0 0 0 0 1 1 0 1 1
Table 19-5. OnCE Command Register (OCMD)
Table 19-6. e200z0 OnCE register addressing
RS[0:6] Register Selected
000 0000–000 0001 Reserved
000 0010 JTAG ID (read-only)
000 0011–000 1111 Reserved
001 0000 CPU Scan Register (CPUSCR)
001 0001 No Register Selected (Bypass)
001 0010 OnCE Control Register (OCR)
001 0011–001 1111 Reserved
010 0000 Instruction Address Compare 1 (IAC1)
010 0001 Instruction Address Compare 2 (IAC2)
010 0010 Instruction Address Compare 3 (IAC3)
010 0011 Instruction Address Compare 4 (IAC4)
010 0100 Data Address Compare 1 (DAC1)
010 0101 Data Address Compare 2 (DAC2)
010 0110 Data Value Compare 1 (DVC1)
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