NXP Semiconductors MPC5606S - Input Programmable Filter (IPF)

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 271
Figure 9-36. OPWMB mode with active output disable
Figure 9-37 shows a waveform changing from 100% to 0% duty cycle. In this case, EDPOL is zero. In this
example, B1 is programmed to the same value as the period of the external selected time base.
Figure 9-37. OPWMB mode from 100% to 0% duty cycle
In Figure 9-37, if B1 is set to a value lower than 0x8, it is not possible to achieve 0% duty cycle by
changing only the A1 register value. Since B1 matches have precedence over A1 matches, the output pin
transitions to the opposite of the EDPOL bit at B1 match. Note also that if for instance B1 is set to 0x9, B1
match does not occur; thus a 0% duty cycle signal is generated.
9.5.1.2 Input Programmable Filter (IPF)
The IPF ensures that only valid input pin transitions are received by the Unified Channel edge detector. A
block diagram of the IPF is shown in
Figure 9-38.
EDPOL = 0
cycle n cycle n+1
cycle n+2
A1 value
B1 value
B2 value
0x000008
0x000002
0x000006
0x000008
0x000001
Selected
0x000004
0x000006
MODE
[6]
= 1
A2 value
0x000002
0x000004
0x000006
0x000002
0x000004
0x000006
0x000008
0x000006
Output pin
write to B2 write to A2
write to A2
Match A1
Match A1
Match B1
Match B1
Match B1
due to B1 match cycle n-1
FLAG set event
Output Disable
Counter Bus
FLAG pin/register
FLAG clear
0x000008
0x000007 0x000006 0x000005
0x000004
0x000003 0x000002
0x000001
0x000000
0%
100%
Selected
EDPOL = 0
A1 value
B1 value
Output pin
0x000008
Prescaler = 1
cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9
counter bus
0x000007
0x000006 0x000005 0x000004
0x000003
0x000002 0x000001
0x000000
A2 value