Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 547
Figure 17-2. Bank 0 Flash Macrocell Structure
17.2.4 Functional description
17.2.4.1 Macrocell structure
The flash module is addressable by word (32 bits) or double-word (64 bits) for program, and page (128
bits) for read. Reads done to the flash module always return 128 bits, although read page buffering may be
done in the platform BIU.
Each read of the flash module retrieves a page, or four consecutive words (128 bits) of information. The
address for each word retrieved within a page differs from the other addresses in the page only by address
bits (3:2).
The flash module supports fault tolerance through Error Correction Code (ECC) and/or error detection.
The ECC implemented within the flash module will correct single bit failures and detect double bit
failures.
The flash module uses an embedded hardware algorithm implemented in the memory interface to program
and erase the flash core.
Control logic that works with the software block enables, and software lock mechanisms, is included in
the embedded hardware algorithm to guard against accidental program/erase commands.
The hardware algorithm perform the steps necessary to ensure that the storage elements are programmed
and erased with sufficient margin to guarantee data integrity and reliability.
A programmed bit in the flash module reads as logic level 0 (or low).
An erased bit in the flash module reads as logic level 1 (or high).
512 KB
+ 16KB Test Flash
HV generator
Flash
Controller
Flash
Matrix
Registers
Program/Erase
Registers
Interface
Flash Bank 0
Interface
+ 16KB Shadow
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