NXP Semiconductors MPC5606S - Interrupt Filter Maximum Counter Registers (IFMC0-IFMC15)

System Integration Unit Lite (SIUL)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1207
37.5.3.15 Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15)
These registers are used to configure the filter counter associated with each digital glitch filter.
37.5.3.16 Interrupt Filter Clock Prescaler Register (IFCPR)
This register is used to configure a clock prescaler which is used to select the clock for all digital filter
counters in the SIUL.
Address: Base + 0x1000–0x103C (16 registers) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0
MAXCNTx[3:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 37-18. Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15)
Table 37-18. IFMC field descriptions
Field Description
MAXCNTx
[3:0]
Maximum Interrupt Filter Counter setting.
Filter Period = T(CK) × MAXCNTx + n × T(CK)
Where (n can be –1 to 3)
MAXCNTx can be 0 to 15
T(CK): Prescaled Filter Clock Period, which is IRC clock prescaled to IFCP value
T(IRC): Basic Filter Clock Period: 62.5 ns (F = 16 MHz)
Address: Base + 0x1080 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0
IFCP[3:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 37-19. Interrupt Filter Clock Prescaler Register (IFCPR)