NXP Semiconductors MPC5606S - Features

IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5606S Microcontroller Reference Manual, Rev. 7
716 Freescale Semiconductor
19.4 Features
The JTAGC is compliant with the IEEE 1149.1-2001 standard, and supports the following features:
• IEEE 1149.1-2001 Test Access Port (TAP) interface
• 4 pins (see Section 19.6, External signal description)
—TDI
—TMS
—TCK
—TDO
• A 5-bit instruction register that supports several IEEE 1149.1-2001 defined instructions, as well as
several public and private MCU specific instructions
• Three test data registers, a bypass register, and a device identification register
• A TAP controller state machine that controls the operation of the data registers, instruction register,
and associated circuitry
19.5 Modes of operation
The JTAGC uses a power-on reset indication as its primary reset signal. Several IEEE 1149.1-2001 defined
test modes are supported, as well as a bypass mode.
19.5.1 Reset
The JTAGC is placed in reset when the TAP controller state machine is in the Test-Logic-Reset state. The
Test-Logic-Reset state is entered upon the assertion of the power-on reset signal, or through TAP controller
state machine transitions controlled by TMS. Asserting power-on reset results in asynchronous entry into
the reset state. While in reset, the following actions occur:
• The TAP controller is forced into the Test-Logic-Reset state, thereby disabling the test logic and
allowing normal operation of the on-chip system logic to continue unhindered.
• The instruction register is loaded with the IDCODE instruction.
In addition, execution of certain instructions can result in assertion of the internal system reset. These
instructions include EXTEST.
19.5.2 IEEE 1149.1-2001 defined test modes
The JTAGC supports several IEEE 1149.1-2001 defined test modes. The test mode is selected by loading
the appropriate instruction into the instruction register while the JTAGC is enabled. Supported test
instructions include EXTEST, SAMPLE, and SAMPLE/PRELOAD. Each instruction defines the set of
data registers that can operate and interact with the on-chip system logic while the instruction is current.
Only one test data register path is enabled to shift data between TDI and TDO for each instruction.
The boundary scan register is external to JTAGC but can be accessed by JTAGC TAP through the
EXTEST, SAMPLE, and SAMPLE/PRELOAD instructions. The functionality of each test mode is
explained in more detail in Section 19.8.4, JTAGC instructions.