Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
254 Freescale Semiconductor
Figure 9-17. eMIOS200 UC Alternate A Register (EMIOSALTA[n])
The EMIOSALTA[n] register provides an alternate address to access A2 channel registers in restricted
modes (GPIO) only. If the EMIOSA[n] register is used along with EMIOSALTA[n], both A1 and A2
registers can be accessed in these modes. Table 9-14 summarizes the EMIOSALTA[n] read and write
accesses for all operation modes.
9.5 Functional description
The eMIOS200 provides independent channels (UC) that can be configured and accessed by a host MCU.
Up to four time bases can be shared by the channels through four counter buses, and each channel can
generate its own time base. Optionally one of the counter buses can be driven by an external time base
imported through the real-time signal interface.
The eMIOS200 module is based on a multi-bus timer architecture in which several timer channels are used
to drive counter buses that are shared among the channels. There are four counter buses in the module: one
global counter bus, shared by all channels and four local counter buses, each one dedicated to a slice of
eight channels. Counter bus A is referred to as the global counter bus. Counter buses B, C, and D are the
local counter buses.
The eMIOS200 counter buses are driven by channels in specific locations. The global counter bus is driven
by the channel in channel slot [23]. Counter buses B, C, and D are driven by channels in slots [0], [8], and
[16], respectively. Counter bus A drives all channels. Counter bus B drives channels in slots from [0]
through [7]. Counter bus C drives channels in slots from [8] through [15]. Counter bus D drives channels
in slots from [16] through [23]. Note that the first channel in an eight-channel slice drives the local counter
bus for that slice—therefore, this channel should not be assigned to be driven by the same counter bus, or
else a loop will occur. The eMIOS200 interrupt request signal, DMA transfer request signal, and others,
are wired to a specific channel—thus the chip integrator should connect those signals having the
eMIOS200 channel configuration in mind.
The eMIOS200 block is reset asynchronously. All registers are cleared on reset.
Figure 9-18 describes an eMIOS200 block configured with 32 Unified Channels. Note that the Red Line
is also present. Note also that independent of the configuration the channels are fixed in their slots. Thus
Address: UC[n] base address + 0x14 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ALTA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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