Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 487
(regardless of the number of implemented channels) provides a global set function, forcing the entire
contents of DMAEEI{H,L} to be asserted. If bit 0 (NOP) is set, the command is ignored. This allows
multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes. See
Figure 15-10 and Table 15-8 for the DMASEEI definition.
15.3.1.8 DMA Clear Enable Error Interrupt (DMACEEI) register
The DMACEEI register provides a simple memory-mapped mechanism to clear a given bit in the
DMAEEI{H,L} registers to disable the error interrupt for a given channel. The data value on a register
write causes the corresponding bit in the DMAEEI{H,L} register to be cleared. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global clear function, forcing the entire
contents of the DMAEEI{H,L} to be zeroed, disabling all DMA request inputs. If bit 0 (NOP) is set, the
command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this
register return all zeroes. See Figure 15-11 and Table 15-9 for the DMACEEI definition.
Address: Base + 0x001A Access: User write-only
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W NOP SEEI[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 15-10. DMA Set Enable Error Interrupt (DMASEEI) register
Table 15-8. DMA Set Enable Error Interrupt (DMASEEI) field descriptions
Name Description
NOP No Operation
0 Normal operation.
1 No operation, ignore bits 6–0
SEEI[0:6] Set Enable Error Interrupt
0–63 Set the corresponding bit in DMAEEI{H,L}
64–127 Set all bits in DMAEEI{H,L}
Address: Base + 0x001B Access: User write-only
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W NOP CEEI[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 15-11. DMA Clear Enable Error Interrupt (DMACEEI) register
Table 15-9. DMA Clear Enable Error Interrupt (DMACEEI) field descriptions
Name Description
NOP No Operation
0 Normal operation.
1 No operation, ignore bits 6–0
CEEI[0:6] Clear Enable Error Interrupt
0–63 Clear corresponding bit in DMAEEI{H,L}
64–127 Clear all bits in DMAEEI{H,L}
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