Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
470 Freescale Semiconductor
Figure 15-1. DMA block diagram
15.2.1 Overview
The DMA is a highly programmable data transfer engine, which has been optimized to minimize the
required intervention from the host processor. It is intended for use in applications where the data size to
be transferred is statically known, and is not defined within the data packet itself. The DMA hardware
supports:
• Single design supporting 16-, 32- and 64-channel implementations, dependent on size of the TCD
memory and design parameters
• Connections to the AMBA-AHB crossbar switch for bus mastering the data movement, slave bus
for programming the module
— Parameterized support for 32- and 64-bit AMBA-AHB datapath widths
• 32-byte transfer control descriptor per channel stored in local memory
• 32 bytes of data registers, used as temporary storage to support burst transfers
j
j+1
n-1
SRAM
Transfer
Control
Descriptor (TCD)
DMA engine
addr_path
data_path
DMA
IPS
Bus
AMBA
AHB
ipd_req[n-1:0]
dma_ipi_int[n-1:0]
0
c
o
n
t
r
o
l
pmodel_charb
addr
wdata[31:0]
rdata[31:0]
hrdata[{63,31}:0]
hwdata[{63,31}:0]
haddr[31:0]
Bus
64
dma_ipd_done[n-1:0]
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