NXP Semiconductors MPC5606S - RAM ECC Address Register (REAR)

Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
538 Freescale Semiconductor
16.4.2.15 RAM ECC Address Register (REAR)
The REAR is a 32-bit register for capturing the address of the last properly enabled ECC event in the RAM
memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM causes the
address, attributes, and data associated with the access to be loaded into the REAR, RESR, REMR, REAT,
and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-14 and Table 16-15 for the RAM ECC Address Register definition.
16.4.2.16 RAM ECC Syndrome Register (RESR)
The RESR is an 8-bit register for capturing the error syndrome of the last properly enabled ECC event in
the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM
causes the address, attributes, and data associated with the access to be loaded into the REAR, RESR,
REMR, REAT, and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register
to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-15 and Table 16-16 for the RAM ECC Syndrome Register definition.
1
Value is undefined at reset.
Table 16-14. Flash ECC Data (FEDR) field descriptions
Name Description
0-31
FEDR[0:31]
Flash ECC Data Register
This 32-bit register contains the data associated with the faulting access of the last properly enabled
flash memory ECC event. The register contains the data value taken directly from the data bus.
Address: Base + 0x0060 Access: User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R REAR[0:15]
W
Reset —
1
1
Value is undefined at reset.
— — — — — — — — — — — — — — —
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R REAR[16:31]
W
Reset — — — — — — — — — — — — — — — —
Figure 16-14. RAM ECC Address Register (REAR)
Table 16-15. RAM ECC Address (REAR) field descriptions
Name Description
0-31
REAR[0:31]
RAM ECC Address Register
This 32-bit register contains the faulting access address of the last properly enabled RAM ECC
event.