NXP Semiconductors MPC5606S - Initialization; Application Information

Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 663
Figure 17-52. 3-cycle access, Abort-and-Retry with Bn_RWWC = 10x
Figure 17-52 shows the abort-while-write timing diagram. In this example, the 3-cycle access to address
y is interrupted when an operation causes the bkn_done signal to be negated signaling that the array bank
is busy with a high-voltage program or erase event. Based on the setting of Bn_RWWC, once the bkn_done
signal is detected as negated, the PFLASH2P_LCA asserts bkn_abort which forces the flash array to
cancel the high-voltage program or erase event. The array operation completes (at the end of cycle 4) and
bkn_done returns to a logical 1. It should be noted that the time spent in cycle 4 for Figure 17-52 is
considerably less than the time in the same cycle in Figure 17-51 (because of the abort operation). In cycle
6, the PFLASH2P_LCA module retries the read to address y which was interrupted by the negation of
bkn_done in cycle 3. Note that throughout cycles 2-9, the AHB bus pipeline is stalled with a read to address
y in the AHB data phase and a read to address y+4 in the address phase. Depending on the state of the
least-significant-bit of the Bn_RWWC control field, the hardware may also signal an abort notification
interrupt (if Bn_RWWC = 100). The stall notification interrupt is shown as the optional assertion of
ECSM’s MIR[FBnAI] (flash bank n abort interrupt).
17.5 Initialization / application information
17.5.1 Background
Flash array access is relatively slow compared to a full speed system clock based on the PLL. To prevent
wait states on every flash access, line buffers are implemented. While wait states are required between the
flash array and line buffer, no wait states are required between a line buffer and the system bus. For
example, if the core is accessing sequential instructions starting at location 0, the first 32 bits (one line)
nonseq
seq
addr y
addr y+4
C(y)
C(y+4)
okay okay okay okay okay okay okay okay
y
C(y)
Burst Read, Abort-and-Retry, APC=2, RWSC=2, PFLM=2
123456
78
addr y
seq
addr y+8
y+16 y+16
y
okay okay
addr y+16addr y (retry)
hclk
htrans
haddr, hprot
hwrite
hrdata
hwdata
hready_out
hresp
bkn_fl_addr
bkn_fl_rd_en
bkn_fl_wr_en
bkn_fl_rdata
bkn_fl_xfr_err
bkn_done
bkn_abort
ECSM_mir[fbnsi]
ECSM_mir[fbnai]
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