Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
748 Freescale Semiconductor
data_received = IBDR// read RX data and store
20.6.1.5 Generation of repeated START
At the end of data transfer, if the master still wants to communicate on the bus, it can generate another
START signal followed by another slave address without first generating a stop signal. A program example
is as shown.
bit 2, IBCR = 1// generate another start ( restart)
IBDR == calling_address// transmit the calling address
20.6.1.6 Slave mode
In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check
if a calling of its own address has just been received. If IAAS is set, software should set the
transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the R/W command bit (SRW). Writing
to the IBCR clears IAAS automatically. Note that the only time IAAS is read as set is from the interrupt
at the end of the address cycle where an address match occurred. Interrupts resulting from subsequent data
transfers will have IAAS cleared. A data transfer may now be initiated by writing information to IBDR for
slave transmits or dummy reading from IBDR in slave receive mode. The slave will drive SCL low
in-between byte transfers SCL is released when the IBDR is accessed in the required mode.
In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the
next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must
be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL
line so that the master can generate a stop signal.
20.6.1.7 Arbitration Lost
If several masters try to engage the bus simultaneously, only one master wins and the others lose
arbitration. The devices that lost arbitration are immediately switched to slave receive mode by the
hardware. Their data output to the SDA line is stopped, but SCL is still generated until the end of the byte
during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer
with IBAL=1 and MS/SL=0. If one master attempts to start transmission, while the bus is being engaged
by another master, the hardware will inhibit the transmission, switch the MS/SL bit from 1 to 0 without
generating a stop condition, generate an interrupt to CPU and set the IBAL to indicate that the attempt to
engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first
and the software should clear the IBAL bit if it is set.
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