NXP Semiconductors MPC5606S - RX FIFO Registers 0 - 14 (QSPI_RXFR0 - QSPI_RXFR14)

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1018 Freescale Semiconductor
30.4.3.10 RX FIFO Registers 0 – 14 (QSPI_RXFR0 – QSPI_RXFR14)
The QSPI_RXFR0–QSPI_RXFR14 registers provide visibility into the RX FIFO for debugging purposes.
Each register is an entry in the RX FIFO. The QSPI_RXFR registers are read-only. Reading the
QSPI_RXFRX registers does not alter the state of the RX FIFO. The RX FIFO implemented has a depth
of 15 entries, so the highest address usable belongs to QSPI_RXFR14. Refer to Table 30-45 for the byte
ordering scheme.
30.4.3.11 Serial Flash Address Register (QSPI_SFAR)
The Serial Flash Address Register contains the address for the next IP command. The number of bits used
from this register depend on the instruction code of the SFM command. See
Section 30.5.3, SFM (Serial
Flash) mode, for details.
Table 30-22. QSPI_TXFRn field descriptions
Field Description
TXCMD TX Command. The TXCMD field contains the command that sets the transfer attributes for the SPI
data. See Section 30.4.3.7, PUSH TX FIFO Register (QSPI_PUSHR), for details on the command
field.
TXDATA TX Data. The TXDATA field contains the SPI data to be shifted out.
Address: QSPI_BASE + 0x07C (QSPI_RXFR0)
...
QSPI_BASE + 0x0B4 (QSPI_RXFR14)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-10. RX FIFO Registers 0 – 14 (QSPI_RXFR0 – QSPI_RXFR14)
Table 30-23. QSPI_RXFRn field descriptions
Field Description
RXDATA RX Data. The RXDATA field contains the received SPI data.