NXP Semiconductors MPC5606S - Memory Map and Register Definition

Sound Generation Logic (SGL)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1111
34.3 Memory map and register definition
34.3.1 Memory map
34.3.2 Register descriptions
34.3.2.1 MODE_SEL register
Table 34-2. SGL memory map
Address Offset Register Access Reset Value
0x00 MODE_SEL register R/W
1
1
Note that read/write registers may contain some read-only or write-only bits.
0x0000_0000
0X04 SOUND_DURATION register R/W 0x0000_0000
0X08 HIGH_PERIOD register R/W 0x0000_0000
0X0C LOW_PERIOD register R/W 0x0000_0000
0X10 SGL_STATUS register R 0x00
Offset 0x00 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
M_P SOUND_CTRL
SDCIE
CH2_SEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PRE CH1_SEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 34-3. MODE_SEL REGISTER
Table 34-3. MODE_SEL field descriptions
Field Description
0
M_P
Selects output corresponding to monophonic or polyphonic sound.
1 Output from and gate will be selected to produce monophonic sound
0 Output from mux A will be selected to produce polyphonic sound
1–3
SOUND_C
TRL
Sound Control bits. See Tabl e 34-10 for a detailed description.