NXP Semiconductors MPC5606S - RAM ECC Data Register (REDR)

Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 541
16.4.2.19 RAM ECC Data Register (REDR)
The REDR is a 32-bit register for capturing the data associated with the last properly enabled ECC event
in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the
RAM causes the address, attributes, and data associated with the access to be loaded into the REAR,
RESR, REMR, REAT, and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status
Register to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-18 and Table 16-20 for the RAM ECC Data Register definition.
Table 16-19. RAM ECC Attributes (REAT) field descriptions
Name Description
0
Write
AMBA-AHB HWRITE
0 AMBA-AHB read access
1 AMBA-AHB write access
1-3
Size[0:2]
AMBA-AHB HSIZE[0:2]
000 8-bit AMBA-AHB access
001 16-bit AMBA-AHB access
010 32-bit AMBA-AHB access
1xx Reserved
4-7
Protection[0:3]
AMBA-AHB HPROT[0:3]
Protection[3]: Cacheable 0 = Non-cacheable, 1 = Cacheable
Protection[2]: Bufferable 0 = Non-bufferable,1 = Bufferable
Protection[1]: Mode 0 = User mode, 1 = Supervisor mode
Protection[0]: Type 0 = I-Fetch, 1 = Data
Address: Base + 0x006C Access: User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R REDR[0:15]
W
Reset —
1
1
Value is undefined at reset.
— — — — — — — — — — — — — — —
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R REDR[16:31]
W
Reset — — — — — — — — — — — — — — — —
Figure 16-18. RAM ECC Data Register (REDR)
Table 16-20. RAM ECC Data (REDR) field descriptions
Name Description
0-31
REDR[0:31]
RAM ECC Data Register
This 32-bit register contains the data associated with the faulting access of the last properly
enabled RAM ECC event. The register contains the data value taken directly from the data bus.