NXP Semiconductors MPC5606S - Low;MID Address Space Block Locking Register (LML)

Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 605
A number of MCR bits are protected against write when another bit, or set of bits, is in a specific state.
These write locks are covered on a bit by bit basis in the preceding description, but those locks do not
consider the effects of trying to write two or more bits simultaneously.
The flash module does not allow the user to write bits simultaneously which would put the device into an
illegal state. This is implemented through a priority mechanism among the bits. The bit changing priorities
are detailed in Table 17-43.
If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority
level will be written.
17.3.6.2 Low/Mid Address Space Block Locking Register (LML)
Address Offset: 0x0004
Reset value: 0x00XXXXXX, initially determined by NVLML value from test sector.
31 EHV: Enable High Voltage (Read/Write)
The EHV bit enables the flash module for a high voltage Program/Erase operation.
EHV is cleared on reset.
EHV must be set after an interlock write to start a Program/Erase sequence. EHV may be set under one
of the following conditions:
Erase (ERS=1, ESUS=0, UT0.AIE=0)
Program (ERS=0, ESUS=0, PGM=1, UT0.AIE=0)
In normal operation, a 1 to 0 transition of EHV with DONE high and ESUS low terminates the current
Program/Erase high voltage operation.
When an operation is aborted, there is a 1 to 0 transition of EHV with DONE low and the eventual Suspend
bit low. An abort causes the value of PEG to be cleared, indicating a failing Program/Erase; address
locations being operated on by the aborted operation contain indeterminate data after an abort. A
suspended operation cannot be aborted.

Aborting a high voltage operation will leave the flash module addresses in an undeterminate data state.
This may be recovered by executing an Erase on the affected blocks.
EHV may be written during Suspend. EHV must be high to exit Suspend. EHV may not be written after
ESUS is set and before DONE transitions high. EHV may not be cleared after ESUS is cleared and before
DONE transitions low.
0: Flash is not enabled to perform an high voltage operation.
1: Flash is enabled to perform an high voltage operation.
Table 17-43. MCR bits set/clear priority levels
Priority level MCR bits
1 ERS
2 PGM
3 EHV
4 ESUS
Table 17-42. MCR field descriptions (continued)
Field Description