NXP Semiconductors MPC5606S - Calculation of FIFO Pointer Addresses-Spi Modes Only

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1059
30.6.5 Calculation of FIFO pointer addresses—SPI modes only
The user has complete visibility of the TX and RX FIFO contents through the FIFO registers, and valid
entries can be identified through a memory-mapped pointer and a memory-mapped counter for each FIFO.
The pointer to the first-in entry in each FIFO is memory-mapped. For the TX FIFO the first-in pointer is
the Transmit Next Pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the Pop Next Pointer
(POPNXTPTR). Figure 30-35 illustrates the concept of first-in and last-in FIFO entries along with the
FIFO Counter. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO.
See Section 30.5.2.5, Transmit First In First Out (TX FIFO) Buffering Mechanism, and Section 30.5.2.6,
Receive First In First Out (RX FIFO) Buffering Mechanism, for details on the FIFO operation.
Table 30-49. Oak family QuadSPI Compatibility with the QuadSPI
Oak family control bits
QuadSPI corresponding control bits
Corresponding QSPI_CTAR Register Setting
BITS
E
CTAS[0
]
DT CTAS[1] DSCK CTAS[2]
QSPI_CTAR
x
FMSZ PDT DT
PCSSC
K
CSSC
K
0 0 0 0 1111 10 0011 00 0000
0 0 1 1 1111 10 0011 user user
0 1 0 2 1111 user
1
1
Selected by user
user 00 0000
0 1 1 3 1111 user user user user
1 0 0 4 user 10 0011 00 0000
1 0 1 5 user 10 0011 user user
1 1 0 6 user user user 00 0000
1 1 1 7 user user user user user