Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
944 Freescale Semiconductor
25.4.3.12 Peripheral Clocks Enable
Based on the current and target device modes, the peripheral configuration registers ME_RUN_PC0…7,
ME_LP_PC0…7, and the peripheral control registers ME_PCTL0…143, the MC_ME enables the clocks
for selected modules as required. This step is executed only after the
Main Voltage Regulator Switch-On
process is completed.
Also if a mode change translates to a startup of one or more power domains, the MC_PCU indicates the
MC_ME after completing the startup sequence upon which the MC_ME may assert the peripheral clock
enables of the peripherals residing in those power domains.
25.4.3.13 Processor and memory clock enable
If the mode transition is from any of the low-power modes Halt or Stop to Run0…3, the clocks to the
processor and system memories are enabled. The process of enabling these clocks is executed only after
the Flash Modules Switch-On process is completed.
25.4.3.14 Processor Low-Power mode exit
If the mode transition is from any of the low-power modes Halt, Stop, or Standby to Run0…3, the MC_ME
requests the processor to exit from its halted or stopped state. This step is executed only after the Processor
and memory clock enable process is completed.
25.4.3.15 System clock switching
Based on the SYSCLK bit field of the ME_<current mode>_MC and ME_<target mode>_MC registers,
if the target and current system clock configurations differ, the following method is implemented for clock
switching.
• The target clock configuration for the 16MHz int. RC osc. is effective only when the S_FIRC bit
of the ME_GS register is set by hardware (i.e. the fast internal RC oscillator (16MHz) has
stabilized).
• The target clock configuration for the div. 16MHz int. RC osc. is effective only when the S_FIRC
bit of the ME_GS register is set by hardware (i.e. the fast internal RC oscillator (16MHz) has
stabilized).
• The target clock configuration for the div. 4-16MHz ext. osc. is effective only when the S_FXOSC
bit of the ME_GS register is set by hardware (i.e the fast external crystal oscillator (4-16MHz) has
stabilized).
• The target clock configuration for the primary freq. mod. PLL is effective only when the
S_FMPLL0 bit of the ME_GS register is set by hardware (i.e. the primary frequency modulated
phase locked loop has stabilized).
• If the clock is to be disabled, the SYSCLK bit field should be programmed with “1111”. This is
possible only in the Stop and Test modes. In the Standby mode, the clock configuration is fixed,
and the system clock is automatically forced to 0.
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