NXP Semiconductors MPC5606S - Effect of Freeze on the Unified Channel

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 273
2. Write the desired value for prescaling rate at the UCPRE[0:1] bits in the EMIOSC[n] register.
3. Enable the channel prescaler by writing 1 at the UCPREN bit in the EMIOSC[n] register.
4. Enable the global prescaler by writing 1 at the GPREN bit in the EMIOSMCR register.
The prescaler is not disabled during freeze state.
9.5.1.4 Effect of Freeze on the Unified Channel
When in debug mode, the FRZ bit in the EMIOSMCR register and the FREN bit in the EMIOSC[n]
register are both set, and the internal counter and the Unified Channel capture and compare functions are
halted. The UC is frozen in its current state.
During freeze, all registers are accessible. When the Unified Channel is operating in an output mode, the
force match functions remain available, allowing the software to force the output to the desired level.
Note that for input modes, any input events that may occur while the channel is frozen are ignored.
When exiting debug mode or when the freeze enable bit is cleared (FRZ in the EMIOSMCR or FREN in
the EMIOSC[n] register), the channel actions resume, but may be inconsistent until the channel enters
GPIO mode again.
9.5.2 IP Bus Interface Unit (BIU)
The BIU provides the interface between the Internal Interface Bus (IIB) and the Peripheral Bus, allowing
communication among all submodules and this IP interface.
The BIU allows 8-, 16-, and 32-bit access. They are performed over a 32-bit data bus in a single cycle
clock.
9.5.2.1 Effect of Freeze on the BIU
When the FRZ bit in the EMIOSMCR register is set and the module is in debug mode, the operation of
BIU is not affected.
9.5.3 Global Clock Prescaler Submodule (GCP)
The GCP divides the system clock to generate a clock for the CPs of the channels. The main clock signal
is prescaled by the value defined in Figure 9-10, according to the GPRE[0:7] bits in the EMIOSMCR
register. The global prescaler is enabled by setting the GPREN bit in the EMIOSMCR register and can be
stopped at any time by clearing this bit, thereby stopping the internal counters in all the channels.
In order to ensure safe working and avoid glitches the following steps must be performed whenever any
update in the prescaling rate is desired:
1. Write 0 to the GPREN bit in the EMIOSMCR register, thus disabling global prescaler.
2. Write the desired value for the prescaling rate to the GPRE[0:7] bits in the EMIOSMCR register.
3. Enable global prescaler by writing 1 to the GPREN bit in the EMIOSMCR register.
The prescaler is not disabled during freeze state.