NXP Semiconductors MPC5606S - Processor Low-Power Mode Entry

Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
942 Freescale Semiconductor
25.4.3.4 Processor Low-Power mode entry
If, on completion of the Peripheral Clocks Disable, the mode transition is to the Halt mode, the MC_ME
requests the processor to enter its halted state. The processor acknowledges its halt state request after
completing all outstanding bus transactions.
If, on completion of the Peripheral Clocks Disable, the mode transition is to the Stop or Standby mode, the
MC_ME requests the processor to enter its stopped state. The processor acknowledges its stop state request
after completing all outstanding bus transactions.
25.4.3.5 Processor and system memory clock disable
If, on completion of the Processor Low-Power mode entry, the mode transition is to the Halt, Stop, or
Standby mode and the processor is in its appropriate halted or stopped state, the MC_ME disables the
processor and system memory clocks to achieve further power saving.
The clocks to the processor and system memories are unaffected for all transitions between software
running modes including DRUN, Run0…3, and Safe.
WARNING
Clocks to the whole device including the processor and system memories
can be disabled in Test mode.
25.4.3.6 Clock sources switch-on
On completion of the Processor Low-Power mode entry, the MC_ME controls all clock sources that affect
the system clock based on the <clock source>ON bits of the ME_<current mode>_MC and
ME_<target mode>_MC registers. The following system clock sources are controlled at this step:
• The fast internal RC oscillator (16MHz)
• The fast external crystal oscillator (4-16MHz)
• The secondary frequency modulated phase locked loop
NOTE
The primary frequency modulated phase locked loop, which needs the main
voltage regulator to be stable, is not controlled by this step.
The clock sources that are required by the target mode are switched on. The duration required for the
output clocks to be stable depends on the type of source, and all further steps of mode transition depending
on one or more of these clocks waits for the stable status of the respective clocks. The availability status
of these system clocks is updated in the S_<clock
source> bits of ME_GS register.
The clock sources which need to be switched off are unaffected during this process in order to not disturb
the system clock which might require one of these clocks before switching to a different target clock.
25.4.3.7 Main Voltage Regulator Switch-On
On completion of the Target mode request, if the main voltage regulator needs to be switched on from its
off state based on the MVRON bit of the ME_<current mode>_MC and ME_<target mode>_MC