NXP Semiconductors MPC5606S - Phase1 Phase

Reset Generation Module (MC_RGM)
MPC5606S Microcontroller Reference Manual, Rev. 7
1090 Freescale Semiconductor
• fast internal RC oscillator (16MHz) clock is running
• All enabled ‘destructive’ resets have been processed
• All processes that need to be done in Phase0 are completed
— FIRC stable, VREG voltage okay
• A minimum of 3 fast internal RC oscillator (16MHz) clock cycles have elapsed since startup
completion and the last enabled ‘destructive’ reset event
31.4.1.2 Phase1 Phase
This phase is entered either on exit from Phase0 or immediately from Phase2, Phase3, or Idle on a
non-masked external or ‘functional’ reset event if it has not been configured to trigger a ‘short’ sequence.
The reset state machine exits Phase1 and enters Phase2 on verification of the following:
• All enabled, non-shortened ‘functional’ resets have been processed
• A minimum of 350 fast internal RC oscillator (16MHz) clock cycles have elapsed since the last
enabled external or non-shortened ‘functional’ reset event
31.4.1.3 Phase2 Phase
This phase is entered on exit from Phase1. The reset state machine exits Phase2 and enters Phase3 on
verification of the following:
• All processes that need to be done in Phase2 are completed
— code and data flash initialization
• A minimum of 8 fast internal RC oscillator (16MHz) clock cycles have elapsed since entering
Phase2
31.4.1.4 Phase3 Phase
This phase is a entered either on exit from Phase2 or immediately from Idle on an enabled, shortened
‘functional’ reset event. The reset state machine exits Phase3 and enters Idle on verification of the
following:
• All processes that need to be done in Phase3 are completed
— code and data flash initialization
• A minimum of 40 fast internal RC oscillator (16MHz) clock cycles have elapsed since the last
enabled, shortened ‘functional’ reset event
31.4.1.5 Idle Phase
This is the final phase and is entered on exit from Phase3. When this phase is reached, the MC_RGM
releases control of the system to the platform and waits for new reset events that can trigger a reset
sequence.