Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
488 Freescale Semiconductor
15.3.1.9 DMA Clear Interrupt Request (DMACINT) register
The DMACINT register provides a simple memory-mapped mechanism to clear a given bit in the
DMAINT{H,L} registers to disable the interrupt request for a given channel. The given value on a register
write causes the corresponding bit in the DMAINT{H,L} register to be cleared. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global clear function, forcing the entire
contents of the DMAINT{H,L} to be zeroed, disabling all DMA interrupt requests. If bit 0 (NOP) is set,
the command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this
register return all zeroes. See Figure 15-12 and Table 15-10 for the DMACINT definition.
15.3.1.10 DMA Clear Error (DMACERR) register
The DMACEER register provides a simple memory-mapped mechanism to clear a given bit in the
DMAERR{H,L} registers to disable the error condition flag for a given channel. The given value on a
register write causes the corresponding bit in the DMAERR{H,L} register to be cleared. A data value of
64 to 127 (regardless of the number of implemented channels) provides a global clear function, forcing the
entire contents of the DMAERR{H,L} to be zeroed, clearing all channel error indicators. If bit 0 (NOP) is
set, the command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of
this register return all zeroes. See Figure 15-13 and Table 15-11 for the DMACERR definition.
Address: Base + 0x001C Access: User write-only
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W NOP CINT[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 15-12. DMA Clear Interrupt Request (DMACINT) fields
Table 15-10. DMA Clear Interrupt Request (DMACINT) field descriptions
Name Description
NOP No Operation
0 Normal operation.
1 No operation, ignore bits 6–0
CINT[0:6] Clear Interrupt Request
0–63 Clear the corresponding bit in DMAINT{H,L}
64–127 Clear all bits in DMAINT{H,L}
Address: Base + 0x001D Access: User write-only
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W NOP CERR[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 15-13. DMA Clear Error (DMACERR) register
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