NXP Semiconductors MPC5606S - Standby Reset Sequence Register (RGM_STDBY)

Reset Generation Module (MC_RGM)
MPC5606S Microcontroller Reference Manual, Rev. 7
1086 Freescale Semiconductor
31.3.1.8 Standby Reset Sequence Register (RGM_STDBY)
This register defines reset sequence to be applied on Standby mode exit. It can be accessed in read/write
in either supervisor mode or test mode. It can be accessed in read only in user mode.
NOTE
This register is reset on any enabled ‘destructive’ or ‘functional’ reset event.
31.3.1.9 Functional Bidirectional Reset Enable Register (RGM_FBRE)
This register enables the generation of an external reset on functional reset. It can be accessed in read/write
in either supervisor mode or test mode. It can be accessed in read in user mode.
Address 0xC3FE_401A Access: Supervisor read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0
BOOT_FROM_BKP_RAM
0 0 0 0 0 0 0
W
reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-9. Standby Reset Sequence Register (RGM_STDBY)
Table 31-10. Standby Reset Sequence Register (RGM_STDBY) field descriptions
Field Description
BOOT_
FROM_
BKP_RAM
Boot from Backup RAM indicator — This bit indicates whether the system will boot from backup RAM or flash
out of Standby exit.
0 Boot from flash on Standby exit
1 Boot from backup RAM on Standby exit
Address 0xC3FE_401C Access: Supervisor read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
BE_EXR
BE_FLASH
BE_LVD45
BE_CMU0_FHL
BE_CMU0_OLR
BE_FMPLL0
BE_CORE
BE_JTAG
W
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-10. Functional Bidirectional Reset Enable Register (RGM_FBRE)