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NXP Semiconductors MPC5606S User Manual

NXP Semiconductors MPC5606S
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FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
670 Freescale Semiconductor
message frames. A flexible number of Message Buffers (16, 32, or 64) is also supported. The Message
Buffers are stored in an embedded RAM dedicated to the FlexCAN module.
The CAN Protocol Interface (CPI) submodule manages the serial communication on the CAN bus,
requesting RAM access for receiving and transmitting message frames, validating received messages, and
performing error handling. The Message Buffer Management (MBM) submodule handles Message Buffer
selection for reception and transmission, taking care of arbitration and ID matching algorithms. The Bus
Interface Unit (BIU) submodule controls the access to and from the internal interface bus, in order to
establish connection to the CPU and to other blocks. Clocks, address and data buses, interrupt outputs, and
test signals are accessed through the Bus Interface Unit.
18.1.2 FlexCAN module features
The FlexCAN module includes these features:
Full implementation of the CAN protocol specification, Version 2.0B
Standard data and remote frames
Extended data and remote frames
0 to 8 bytes data length
Programmable bit rate up to 1 Mb/s
Content-related addressing
Flexible Message Buffers (up to 64) of 0 to 8 bytes data length
Each MB configurable as Rx or Tx, all supporting standard and extended messages
Individual Rx Mask registers per Message Buffer
Includes either 1056 bytes (64 MBs) of RAM used for MB storage
Includes either 256 bytes (64 MBs) of RAM used for individual Rx Mask registers
Full featured Rx FIFO with storage capacity for six frames and internal pointer handling
Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 8 extended, 16
standard, or 32 partial (8 bits) IDs, with individual masking capability
Selectable backwards compatibility with previous FlexCAN version
Programmable clock source to the CAN Protocol Interface (CPI), either bus clock or crystal
oscillator
Unused MB and Rx Mask register space can be used as general-purpose RAM space
Listen-only mode capability
Programmable loopback mode supporting self-test operation
Programmable transmission priority scheme: lowest ID, lowest buffer number, or highest priority
Time stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Independent of the transmission medium (an external transceiver is assumed)
Short latency time due to an arbitration scheme for high-priority messages

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NXP Semiconductors MPC5606S Specifications

General IconGeneral
BrandNXP Semiconductors
ModelMPC5606S
CategoryMicrocontrollers
LanguageEnglish

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