NXP Semiconductors MPC5606S - Interrupt Mask Register (INT_MASK)

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 373
12.3.4.20 Interrupt Mask Register (INT_MASK)
Figure 12-22 represents the interrupt mask register.This register enables or masks corresponding interrupt.
23
P2_FIFO_LO_FLAG
Interrupt signal that indicates the Low threshold has been reached for plane 2 (FGplane)
input buffer
24
P1_FIFO_HI_FLAG
Interrupt signal that indicates the High threshold has been reached for plane 1 (BGplane)
input buffer
25
P1_FIFO_LO_FLAG
Interrupt signal that indicates the Low threshold has been reached for plane 1 (BGplane)
input buffer
26
CRC_OVERFLOW
Interrupt signal that indicates the CRC_ready has not been serviced and CRC has been
calculated for the next frame
27
CRC_READY
Interrupt signal to indicate CRC calculation is done and ready to be compared with
precomputed CRC value by the software
28
VS_BLANK
Interrupt signal to indicate vertical blanking period. This is the period in which all the
registers that affect the visible state of the layers need to be latched. This is needed so
that CPU writes to the register while the display is being updated does not cause any
errors.
29
LS_BF_VS
Lines Before Vsync interrupt. It is generated threshold LS_BF_VS number of lines ahead
of the vertical front porch (FP_V) if enabled. The CPU can program the registers after
LS_BF_VS interrupt.
30
UNDRUN
Under Run Exception Interrupt. Asserted when display needs data and output buffer filling
is lower than or equal to the OUT_BUF_LOW threshold. Interrupt is cleared when the data
in the output buffer is greater than threshold and CPU writes 1 to this bit.
31
VSYNC
Vertical Synchronize Interrupt. If enabled, an interrupt is generated at the beginning of a
frame.
Table 12-23. INT_STATUS field descriptions (continued)
Field Description