IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 715
Chapter 19
IEEE 1149.1 Test Access Port Controller (JTAGC)
19.1 Introduction
The JTAG port of the device consists of three inputs and one output. These pins include test data input
(TDI), test data output (TDO), test mode select (TMS), and test clock input (TCK). TDI, TDO, TMS, and
TCK are compliant with the IEEE 1149.1-2001 standard and are shared with the NDI through the test
access port (TAP) interface.
IEEE 1149.7 (cJTAG) is not supported on this device.
19.2 Block diagram
Figure 19-1 is a block diagram of the JTAG Controller (JTAGC).
Figure 19-1. JTAG controller block diagram
19.3 Overview
The JTAGC provides the means to test chip functionality and connectivity while remaining transparent to
system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the
IEEE 1149.1-2001 standard. In addition, instructions can be executed that allow the Test Access Port
(TAP) to be shared with other modules on the MCU. All data input to and output from the JTAGC is
communicated in serial format.
TCK
TMS
TDI
Test access port (TAP)
TDO
32-bit device identification register
Boundary scan register
controller
1-bit bypass register
5-bit TAP instruction decoder
5-bit TAP instruction register
Power-on
reset
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