NXP Semiconductors MPC5606S - Functional Description

Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 307
Table 11-17 describes the field in the DSPI receive FIFO register.
11.8 Functional description
The DSPI supports full-duplex, synchronous serial communications between the MCU and peripheral
devices. All communications are through an SPI-like protocol.
The DSPI has one configuration:
• Serial peripheral interface (SPI) configuration in which the DSPI operates as a basic SPI or a
queued SPI
The DCONF field in the DSPIx_MCR register determines the DSPI configuration. Refer to Table 11-3 for
the DSPI configuration values.
The DSPIx_CTAR0–DSPIx_CTAR7 registers hold clock and transfer attributes.The SPI configuration can
select which CTAR to use on a frame-by-frame basis by setting the CTAS field in the DSPIx_PUSHR.
The 16-bit shift register in the master and the 16-bit shift register in the slave are linked by the SOUT_x
and SIN_x signals to form a distributed 32-bit register. When a data transfer operation is performed, data
is serially shifted a predetermined number of bit positions. Because the registers are linked, data is
exchanged between the master and the slave; the data that was in the master’s shift register is now in the
Address: 
Base + 0x007C (DSPIx_RXFR0)
Base + 0x0080 (DSPIx_RXFR1)
Base + 0x0084 (DSPIx_RXFR2)
Base + 0x0088 (DSPIx_RXFR3)
Base + 0x008C (DSPIx_RXFR4)
Access: R/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-10. DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn)
Table 11-17. DSPIx_RXFRn field descriptions
Field Description
0–15 Reserved, must be cleared.
16–31
RXDATA
[15:0]
Receive data. Contains the received SPI data.