NXP Semiconductors MPC5606S - Output Clock Multiplexing

Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
208 Freescale Semiconductor
8.4.4.2.2 Auxiliary clock dividers
The selected auxiliary clock can be optionally divided before use.
8.4.4.2.3 Dividers functional description
Dividers are used for the generation of divided system and peripheral clocks. The MC_CGM has the
following control registers for built-in dividers:
• Section 8.4.3.1.4, System Clock Divider Configuration Registers (CGM_SC_DC0…2)
• Section 8.4.3.1.7, Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)
• Section 8.4.3.1.9, Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)
The reset value of all counters is 1. If a divider has its DE bit in the respective configuration register set to
0 (the divider is disabled), any value in its DIVn field is ignored.
8.4.4.3 Output clock multiplexing
The MC_CGM contains a multiplexing function for a number of clock sources which can then be used as
output clock sources. The selection is done via the CGM_OCDS_SC register.
Figure 8-18. MC_CGM Output Clock Multiplexer and PH[4] Generation
8.4.4.4 Output Clock Division Selection
The MC_CGM provides the following output signals for the output clock generation:
• PH[4] (see Figure 8-18). This signal is generated by using one of the 3-stage ripple counter outputs
or the selected signal without division. The non-divided signal is not guaranteed to be 50% duty
cycle by the MC_CGM.
• The MC_CGM also has an output clock enable register (see Section 8.4.3.1.1, Output Clock
Enable Register (CGM_OC_EN)), which contains the output clock enable/disable control bit.
CGM_OCDS_SC.SELCTL
CGM_OCDS_SC.SELDIV
0
1
2
3
Register
Register
16 MHz internal RC oscillator 0
4–16 MHz external oscillator 1
Primary FMPLL 2
Secondary FMPLL 3
128 kHz internal RC oscillator 4
32 kHz external oscillator 5
PH[4]
’0’
CGM_OC_EN Register