Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 525
programming model must match the size of the register, for example, an n-bit register only supports n-bit
writes, etc. Attempted writes of a different size than the register width produce an error termination of the
bus cycle and no change to the targeted register.
16.4.2.1 Processor Core Type (PCT) register
The PCT is a 16-bit read-only register specifying the architecture of the processor core in the device. The
state of this register is defined by a module input signal; it can only be read from the IPS programming
model. Any attempted write is ignored.
See Figure 16-1 and Table 16-2 for the Processor Core Type definition.
16.4.2.2 Revision (REV) register
The REV is a 16-bit read-only register specifying a revision number that can only be read from the IPS
programming model. Any attempted write is ignored.
See Figure 16-2 and Table 16-3 for the Revision definition.
16.4.2.3 Miscellaneous Reset Status Register (MRSR)
The MRSR contains a bit for each of the reset sources to the device. An asserted bit indicates the last type
of reset that occurred. Only one bit is set at any time in the MRSR, reflecting the cause of the most recent
Address: Base + 0x0000 Access: User read-only
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R PCT[0:15]
W
Reset 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0
Figure 16-1. Processor Core Type (PCT) register
Table 16-2. Processor Core Type (PCT) field descriptions
Name Description
0-15
PCT[0:15]
Processor Core Type
0xE012 identifies the e200z0h Power Architecture processor core.
Address: Base + 0x0002 Access: User read-only
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R REV[0:15]
W
Reset REV[0:15]
Figure 16-2. Revision (REV) register
Table 16-3. Revision (REV) field descriptions
Name Description
0-15
REV[0:15]
Revision
The REV[0:15] field is specified by an input signal to define a software-visible revision number.
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