NXP Semiconductors MPC5606S - Flash ECC Data Register (FEDR)

Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 537
16.4.2.14 Flash ECC Data Register (FEDR)
The FEDR is a 32-bit register for capturing the data associated with the last properly enabled ECC event
in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash
memory causes the address, attributes, and data associated with the access to be loaded into the FEAR,
FEMR, FEAT, and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register
to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-13 and Table 16-14 for the Flash ECC Data Register definition.
Address: Base + 0x0057 Access: User read-only
0 1 2 3 4 5 6 7
R Write Size[0:2] Protection[0:3]
W
Reset —
1
1
Value is undefined at reset.
— — — — — — —
Figure 16-12. Flash ECC Attributes (FEAT) register
Table 16-13. Flash ECC Attributes (FEAT) field descriptions
Name Description
0
Write
AMBA-AHB HWRITE
0 AMBA-AHB read access
1 AMBA-AHB write access
1-3
Size[0:2]
AMBA-AHB HSIZE[0:2]
000 8-bit AMBA-AHB access
001 16-bit AMBA-AHB access
010 32-bit AMBA-AHB access
1xx Reserved
4-7
Protection[0:3]
AMBA-AHB HPROT[0:3]
Protection[3]: Cacheable 0 = Non-cacheable,1 = Cacheable
Protection[2]: Bufferable 0 = Non-bufferable,1 = Bufferable
Protection[1]: Mode 0 = User mode, 1 = Supervisor mode
Protection[0]: Type 0 = I-Fetch, 1 = Data
Address: Base + 0x005C Access: User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R FEDR[0:15]
W
Reset —
1
— — — — — — — — — — — — — — —
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R FEDR[16:31]
W
Reset — — — — — — — — — — — — — — — —
Figure 16-13. Flash ECC Data Register (FEDR)