NXP Semiconductors MPC5606S - External Interrupts

System Integration Unit Lite (SIUL)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1209
Figure 37-20. Data Port example arrangement showing configuration for different port width accesses
This implementation requires that the registers are arranged in such a way as to support this range of port
widths without having to split reads or writes into multiple accesses.
The SIUL has separate data input (GPDIn_n, see Section 37.5.3.11, GPIO Pad Data Input Registers
(GPDI0_3–GPDI132_135)) and data output (GPDOn_n, see Section 37.5.3.10, GPIO Pad Data Output
Registers (GPDO0_3–GPDO132_135)) registers for all pads, allowing the possibility of reading back an
input or output value of a pad directly. This supports the ability to validate what is present on the pad rather
than simply confirming the value that was written to the data register by accessing the data input registers.
The data output registers support both read and write operations to be performed.
The data input registers support read access only.
When the pad is configured to use one of its alternate functions, the data input value reflect the respective
value of the pad. If a write operation is performed to the data output register for a pad configured as an
alternate function (non GPIO), this write will not be reflected by the pad value until reconfigured to GPIO.
The allocation of what input function is connected to the pin is defined by the PSMI registers (PCRn, see
Section 37.5.3.8, Pad Configuration Registers (PCR0–PCR132)).
37.6.4 External interrupts
The SIUL supports 14 external interrupts, EIRQ0–EIRQ13. See Table 37-1 for the map of the external
interrupts on the external pins.
The SIUL supports two interrupt vectors to the interrupt controller. Each vector interrupt has up to eight
external interrupts combined together with the presence of flag generating an interrupt for that vector if
enabled. All of the external interrupt pads within a single group have equal priority.
See Figure 37-21 for an overview of the External Interrupt implementation.
31
23
SIU Base+ 0x0000
15 7 0
SIU Base+
15 7 0
SIU Base+
15 7 0
SIU Base+
70
0x0003
SIU Base+
70
0x0002
SIU Base+
70
0x0001
SIU Base+
70
0x0000
0x0002
0x0000
32-bit Port
16-bit Port
16-bit Port
8-bit Port
8-bit Port
8-bit Port
8-bit Port