NXP Semiconductors MPC5606S - DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) Registers

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
484 Freescale Semiconductor
As a given channel completes the processing of its major iteration count, there is a flag in the transfer
control descriptor that may affect the ending state of the DMAERQ bit for that channel. If the TCD.d_req
bit is set, then the corresponding DMAERQ bit is cleared, disabling the DMA request; else if the d_req bit
is cleared, the state of the DMAERQ bit is unaffected.
15.3.1.4 DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) registers
The DMAEEI{H,L} registers provide a bit map for the implemented channels {16,32,64} to enable the
error interrupt signal for each channel. DMAEEIH supports channels 63-32, while DMAEEIL covers
channels 31-00. The state of any given channel’s error interrupt enable is directly affected by writes to this
register; it is also affected by writes to the DMASEEI and DMACEEI registers. The DMA{S,C}EEI
registers are provided so that the error interrupt enable for a single channel can easily be modified without
the need to perform a read-modify-write sequence to the DMAEEI{H,L} registers.
Both the DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt
request for a given channel is asserted. See Figure 15-6, Figure 15-7, and Table 15-5 for the DMAEEI
definition.
Address: Base + 0x000C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ERQ
31
ERQ
30
ERQ
29
ERQ
28
ERQ
27
ERQ
26
ERQ
25
ERQ
24
ERQ
23
ERQ
22
ERQ
21
ERQ
20
ERQ
19
ERQ
18
ERQ
17
ERQ
16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ERQ
15
ERQ
14
ERQ
13
ERQ
12
ERQ
11
ERQ
10
ERQ
09
ERQ
08
ERQ
07
ERQ
06
ERQ
05
ERQ
04
ERQ
03
ERQ
02
ERQ
01
ERQ
00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-5. DMA Enable Request Low (DMAERQL) register
Table 15-4. DMA Enable Request (DMAERQH, DMAERQL) field descriptions
Name Description
ERQn,
n = 0,... 15
n = 0,... 31
n = 0,... 63
Enable DMA Request n
0 The DMA request signal for channel n is disabled.
1 The DMA request signal for channel n is enabled.