Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
276 Freescale Semiconductor
Figure 9-42. Time base generation with internal clock and clear on match start
Figure 9-43. Time base generation with clear on match end
9.6.2.2 Coherent accesses
The FLAG set event can be detected by polling the FLAG bit or by enabling the interrupt or DMA request
generation.
Reading the EMIOSA[n] register again in the same period as the last read of the EMIOSB[n] register may
lead to incoherent results. This will occur if the last read of the EMIOSB[n] register occurred after a
disabled B2 to B1 transfer.
9.6.2.3 Channel/modes initialization
The following basic steps summarize basic output mode startup, assuming the channels are initially in
GPIO mode:
1. [global] Disable the Global Prescaler.
2. [timebase channel] Disable the Channel Prescaler.
3. [timebase channel] Write the initial value to the internal counter.
4. [timebase channel] Set A/B register.
system clock
prescaler clock enable
internal counter
match value = 3
0 13
0
2 0
3
0
PRESCALED CLOCK RATIO = 3
see note 1
Note 1: When a match occurs, the first clock cycle is used to clear the
1
2
FLAG set event
FLAG clear
FLAG pin/register
system clock
input event/prescaler clock enable
internal counter
match value = 3
0 13
2 0
PRESCALED CLOCK RATIO = 3
see note 1
Note 1: The match occurs only when the input event/prescaler clock enable is active.
Then, the internal counter is immediately cleared.
1
2
3
FLAG set event
FLAG clear
FLAG pin/register
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