NXP Semiconductors MPC5606S - Page 277

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 275
Figure 9-40. Time base period when running in the fastest prescaler ratio
If the prescaler ratio is greater than one or if the external clock is selected, the counter may behave in three
different ways, depending on the channel mode:
• If MC mode and Clear on Match Start and External Clock source are selected, the internal counter
behaves as shown in Figure 9-41.
• If MC mode and Clear on Match Start and Internal Clock source are selected, the internal counter
behaves as shown in Figure 9-42.
• If MC mode and Clear on Match End are selected, the internal counter behaves as shown in
Figure 9-43.
• If OPWFM mode is selected, the internal counter behaves as shown in Figure 9-42. The internal
counter clears at the start of the match signal, skips the next prescaled clock edge, and then
increments on the subsequent prescaled clock edge.
NOTE
MCB and OPWFMB modes have different behavior.
Figure 9-41. Time base generation with external clock and clear on match start
system clock
input event/prescaler clock enable = 1
internal counter
match value = 3
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
PRE SCALED CLOCK RATIO = 1 (bypassed)
see note 1
FLAG set event
Note 1: When a match occurs, the first clock cycle is used to
clear the internal counter, starting another period.
FLAG pin/register
FLAG clear
system clock
input event
internal counter
match value = 3
1 23
0
see note 1
Note 1: When a match occurs, the first system clock cycle is used to clear the
internal counter, and at the next edge of prescaler clock enable
1
2
the counter will start counting.
1 23
0
FLAG set event
FLAG clear
FLAG pin/register