Wakeup Unit (WKPU)
MPC5606S Microcontroller Reference Manual, Rev. 7
1246 Freescale Semiconductor
The Wakeup Unit supports the generation of three types of interrupts from the NMI. The Wakeup Unit
supports the capturing of a second event per NMI input before the interrupt is cleared, thus reducing the
chance of losing an NMI event.
Each NMI passes through a bypassable analog glitch filter.
NOTE
Glitch filter control and pad configuration should be done while the NMI is
disabled in order to avoid erroneous triggering by glitches caused by the
configuration process itself.
Figure 41-11. NMI Pad Diagram
41.5.2.1 NMI Management
The NMI can be enabled or disabled using the single NCR register laid out to contain all configuration bits
for an NMI in a single byte (see
Figure 41-3). The pad defined as an NMI can be configured by the user
to recognize interrupts with an active rising edge, an active falling edge or both edges being active. A
setting of having both edge events disabled results in no interrupt being detected and should not be
configured.
The active NMI edge is controlled by the user through the configuration of the NREE and NFEE bits.
Glitch Filter
Edge Detect
Flag Overrun
Destination
NMI
critical IRQ
machine check
Wakeup Enable
CPU
Mode/
Pwr Ctl
NDSS
NWRE
NREE
NFEE
NFE
NMI Configuration Register (NCR)
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