NXP Semiconductors MPC5606S - Continuous Serial Communications Clock

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1045
30.5.2.9 Continuous Serial Communications Clock
The QuadSPI provides the option of generating a continuous SCK signal for slave peripherals that require
a continuous clock.
Continuous SCK is enabled by setting the CONT_SCKE bit in the QSPI_MCR. Continuous SCK is valid
in both SPI modes.
Continuous SCK is only supported for CPHA=1. Setting CPHA=0 will be ignored if the CONT_SCKE bit
is set. Continuous SCK is supported for Modified Transfer Format.
Clock and transfer attributes for the Continuous SCK mode are set according to the following rules:
• In both SPI modes CTAR0 shall be used initially. At the start of each SPI frame transfer, the CTAR
specified by the CTAS for the frame shall be used.
• In both SPI modes the currently selected CTAR shall remain in use until the start of a frame with
a different CTAR specified, or the Continuous SCK mode is terminated.
It is recommended that the baud rate is the same for all transfers made while using the Continuous SCK.
Switching clock polarity between frames while using Continuous SCK can cause errors in the transfer.
Continuous SCK operation is not guaranteed if the QuadSPI is put into the Stop mode or Module Disable
mode.
Enabling Continuous SCK disables the PCS to SCK delay and the Delay after Transfer (T
DT
) is fixed at
one T
SCK
cycle. Figure 30-33 shows timing diagram for Continuous SCK format with Continuous
Selection disabled.
Figure 30-33. Continuous SCK Timing Diagram (CONT=0)
If the CONT bit in the TX FIFO entry is set PCS remains asserted between the transfers. Under certain
conditions, SCK can continue with PCS asserted, but with no data being shifted out of SO (SO pulled
high). This can cause the slave to receive incorrect data. Those conditions include:
• Continuous SCK with CONT bit set, but no data in the transmit FIFO.
• Continuous SCK with CONT bit set and entering Stopped state (refer to Section 30.5.2.1, Start and
Stop of SPI Transfers).
t
DT
SCK
PCS
SCK
Master SO
Master SI
(CPOL = 0)
(CPOL = 1)